Publications

◾T. Mahfuz, S. Paria, T. Suha, S. Bhunia, and P. Chakraborty. "POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage." in 2025 62nd ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2025. (Accepted, awaiting publication)

◾S. Paria, A. Dasgupta, and S. Bhunia. "Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages." in 2025 IEEE 43rd VLSI Test Symposium (VTS), Tempe, AZ, USA, 2024. (Accepted, awaiting publication)

◾S. Paria*, D. Ankireddy*, A. Dasgupta, and S. Bhunia. "CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking." in 2025 IEEE 43rd VLSI Test Symposium (VTS), Tempe, AZ, USA, 2024. (Accepted, awaiting publication)  *Equal Contribution

◾S. Paria, P. Gaikwad, A. Dasgupta, and S. Bhunia. "LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection." in 2024 IEEE 33rd Asian Test Symposium (ATS), Ahmedabad, India, 2024. [Click here]

◾M. Rahman, R. Almawzan, A. Dasgupta, S. Paria, and S. Bhunia. "United We Protect: Protecting IP Confidentiality with Integrated Transformation and Redaction.'" 2024 IEEE Physical Assurance and Inspection of Electronics (PAINE), Huntsville, AL, USA, 2024. [Click here] 

◾A. Dasgupta, S. Paria, P. Chakraborty, and S. Bhunia. "Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs." 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA, 2024. [Click here]

◾R. Almawzan, S. Paria, A. Dasgupta, K. Amberiadis, and S. Bhunia. "IP Security in Structured ASIC: Challenges and Prospects." 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA, 2024. [Click here]

◾S. Paria, A. Dasgupta, and S. Bhunia. 2024. "Navigating SoC Security Landscape on LLM-Guided Paths." In Proceedings of the Great Lakes Symposium on VLSI 2024 (GLSVLSI ’24), pp. 252-257. [Click here]

◾S. Paria, A. Dasgupta and S. Bhunia, "DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement." 2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Tysons Corner, VA, USA, 2024, pp. 271-281. [Click here]

◾A. Dutta, S. Paria, T. Golui, and D. K. Kole, "Structural analysis and regular expressions based noise elimination from web pages for web content mining." 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Delhi, India, 2014, pp. 1445-1451. [Click here]

◾A. Dutta, S. Paria, T. Golui, and D. K. Kole. "Noise Elimination from Web Page Based on Regular Expressions for Web Content Mining." Advanced Computing, Networking and Informatics- Volume 1, pp. 545-554, ICACNI-2014, Springer Digital Library, June 2014. [Click here]

◾A. Dasgupta, S. Paria, and S. Bhunia. "HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction." in IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025 (Vol. 3). (Accepted, awaiting publication)

◾S. Paria, A. Dasgupta, and S. Bhunia. "SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems." in IEEE Embedded Systems Letters, Aug 2024, doi: 10.1109/LES.2024.3447691. [Click here]

◾R. Sadhukhan, S. Saha, S. Paria, S. Bhunia, and D. Mukhopadhyay, "VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection." in IEEE Transactions on Computers, vol. 73, no. 2, pp. 436-450. [Click here]

◾S Bhunia, PD Gaikwad, JW Cruz, S Paria, "Invisible scan architecture for secure testing of digital designs", US Patent 11,953,548, 2024. [Click here] 

◾R. Saravanan, S. Paria, A. Dasgupta, V. N. Patnala, S. Bhunia, Sai Manoj P. D. "SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs." arXiv preprint arXiv:2504.18812. [Click here] 

◾A. Dasgupta, S. Paria, and S. Bhunia. "HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction." Cryptology ePrint Archive, Paper 2025/553, 2025. [Click here]  

◾S. Paria, A. Dasgupta, and S. Bhunia. "Post-Silicon Hardware Trojan Detection with High Confidence Leveraging Automated Test Patterns." in GOMACTech 2025. [Click here]

◾A. Dasgupta, S. Paria, C. Sozio, A. Lukefahr, and S. Bhunia. (2025). "Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection." arXiv preprint 2501.12292. [Click here]

◾S. Paria, A. Dasgupta, and S. Bhunia. (2023). "DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection." ArXiv, abs/2308.06932. [Click here] 

◾S. Paria and S. Bhunia. (2023). "DiSPEL: Distributed Security Policy Enforcement for Bus-based SoC." arXiv preprint arXiv:2308.02792. [Click here] 

◾Swarup Bhunia and Mark Tehranipoor. 2018. Hardware Security: A Hands-on Learning Approach (2nd. ed.). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA. [Click here] 

Contributions: 

Chapter 5: Hardware Trojans 

Chapter 13: Security and Trust Assessment and Design for Security

Chapter 14: Hardware Obfuscation 

Chapter 16: System Level Attacks & Countermeasures