Research Projects

Sudipta Paria is primarily working on the broad field of Hardware Security & Trust, focusing on developing innovative CAD tools for automation while also exploring the integration of AI and ML techniques to enhance system security. The major objective is to address critical security challenges within the integrated circuit (IC) supply chain, particularly in the context of the modern zero-trust model. His research interests include but are not limited to the following topics:

◾ Hardware Intellectual Property (IP) Security and Trust

◾ Hardware Obfuscation and Redaction, Logic Locking

◾ Computer-Aided-Design (CAD) Tools

◾ Machine Learning in EDA

◾ Generative AI in SoC Security and Trust

◾ Scan Chain Protection and Secure Testing

◾ Formal Verification

◾ Fuzzing

◾ Hardware Trojans

 ..... and many more.

▶  DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement 

◾ Developed an automated framework for enforcing system-level security requirements via synthesizable security policies within acceptable overhead constraints using a feedback path to discard lower-ranked policies.

◾ Specifying diverse security policies represented in a high-level 3-tuple representation with reconfigurability makes it extendable to any bus-based SoC for various threat models and trust assumptions. 

◾ A hybrid approach to incorporate diverse bus-level security policies involving multiple IPs through a centralized policy module and IP-level policies through bus-level wrappers.

▶  DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection 

◾ Developed an automation framework for generating queries from user-given specifications and security requirements to identify CWEs by leveraging the LLM knowledge base for any generic bus-based SoC. 

◾ Curated an extensive list of CWEs with different classifications for bus-level and IP-level vulnerabilities, and incorporated a novel filtering methodology to retain only relevant CWEs for a given SoC context.

◾ Analyzing and correcting SVAs generated by LLMs for a target SoC and converting SVAs to respective security policies, followed by enforcing through a centralized security module or bus-level wrapper based on the security specifications. 

▶  LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection

◾ An efficient and robust HT detection framework that leverages automated test pattern generation that satisfies the N-detect principle of activating rare nodes through SCOAP values-based rareness analysis.

◾ Combining non-conflicting rare nodes using fan-in cone and PI analysis, followed by a heuristic-based vector generation method for generating an optimal number of simulation vectors for coverage analysis through payload-aware hardware Trojans.  

▶  SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs

◾ Proposed novel hardware fuzzer that leverages state-of-the-art gate-level fuzzing at post-synthesis level to unveil RTL, synthesis, and library bugs.

◾ Introduced a new class of synthesis attack model, CLiMA, leveraging malicious library mapping through the logic synthesis tools, and discovered seven new synthesis bugs in open-source CPU designs.

▶  POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage

◾ Developed a novel explainable design-for-security framework for mitigating power side-channel vulnerabilities in electronic systems and integrated it into the ASIC design flow.

◾ Designed an unsupervised algorithm to automatically generate training data for POLARIS using a search approach leveraging xAI algorithm for efficiently masking a given digital design.

▶  LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency

◾ Developed a circuit-level scan instrumentation technique that incorporates low-overhead additional logic that uses standard cell library elements into the scan flip-flops to improve testability, which can be seamlessly integrated with commercial DFT tool flow.

◾ Experimental evaluation using a suite of ISCAS89 and ITC99 benchmarks shows that LITE can improve the ATPG test pattern count by about 31% and also effectively address the coverage issues arising from the random-resistant faults,  thereby improving the random pattern testability of the designs.

▶  LASSO: LM-Aided Security Property Generation for Assertion-based SoC Verification

◾ Developed a novel and efficient framework that leverages the knowledge base of LLMs to automatically generate security properties and SVAs, enabling comprehensive verification of generic bus-based SoC designs.

◾ Integrated vacuity checking for identifying and discarding vacuous or non-meaningful properties to enhance verification efficiency and reduce the computational overhead. 

◾ Experimental results demonstrate the effectiveness by evaluating on open-source SoC benchmarks, achieving high coverage values that indicate substantial verification performance along with bug detection capabilities, as evidenced by the identification of five bugs in the buggy OpenTitan benchmark.

▶  CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking

◾ Developed a novel structural analysis-based scalable cut-point matching framework that can be seamlessly integrated into commercial EDA solutions to perform enhanced logic equivalence checking.

◾ CLIP outperforms state-of-the-art LEC techniques using commercial EDA tools in terms of cut-point matching in diverse verification scenarios, including resynthesis, name changes, technology transfer, and transformations through hardware obfuscation techniques across five diverse open-source benchmark suites.

▶  Invisible Scan for Protecting Against Scan-Based Attacks 

◾ Developed a novel scan-protection architecture and corresponding design methodology for protecting the scan chain against reverse engineering attacks utilizing state space obfuscation approach.

◾ Evaluated fault coverage after incorporating InvisibleScan on the open-source benchmarks and analyzing performance and security protection against scan-based confidentiality and RE attacks. 

◾"Mitigating Fault Attack Vulnerabilities in Block Ciphers through automated insertion of Fault Tolerant Techniques", M.Tech Thesis (2020)

◾"Developing Predictive Model to identify Risky Devices", IBM Internship (2019) 

◾"Developing an Online Course Portal", Infosys Campus Connect (2014)

◾"Eliminating noisy information and Coherent Key-phrase Extraction from web pages", B.Tech Final year project (2014)

◾Detecting Hardware Trojans using Graph Neural Networks in RTL and Gate-Level Designs (2022) 

◾Creating a basic online IDE with Live Parser (2019)

◾Sentiment Analysis of IMDB Movie Reviews (2019) 

◾Multi-user P2P Chat Application with File Sharing (2019) 

◾Predicting the helpfulness of Amazon Reviews (2018)