Research Projects

Sudipta Paria is primarily working on the broad field of Hardware Security & Trust, focusing on developing innovative CAD tools for automation while also exploring the integration of AI and ML techniques to enhance system security. The major objective is to address critical security challenges within the integrated circuit (IC) supply chain, particularly in the context of modern zero-trust model. His research interest includes but is not limited to the following topics:

◾Hardware Intellectual Property (IP) Security and Trust

◾Hardware Obfuscation and Redaction, Logic Locking

◾Computer-Aided-Design (CAD) Tools

◾Machine Learning in EDA

◾Generative AI in SoC Security and Trust

◾Scan Chain Protection and Secure Testing

◾Formal Verification

◾Hardware Trojans

 ..... and many more.

▶  DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement 

◾An automated framework for enforcing system-level security requirements via synthesizable security policies within acceptable overhead constraints using a feedback path to discard lower-ranked policies.

◾Specifying diverse security policies represented in a high-level 3-tuple representation with reconfigurability makes it extendable to any bus-based SoC for various threat models and trust assumptions. 

◾A hybrid approach to incorporate diverse bus-level security policies involving multiple IPs through a centralized policy module and IP-level policies through bus-level wrappers.

▶  DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection 

◾An automation framework for generating queries from user-given specifications and security requirements to identify CWEs by leveraging the LLM knowledge base for any generic bus-based SoC. 

◾Curating an extensive list of CWEs with different classifications for bus-level and IP-level vulnerabilities and incorporating a filtering methodology to retain only relevant CWEs for a given SoC context.

◾Analyzing and correcting SVAs generated by LLMs for a target SoC and converting SVAs to respective security policies followed by enforcing through a centralized security module or bus-level wrapper based on the security specifications. 

▶  LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection

◾An efficient and robust HT detection framework that leverages on automated test pattern generation approach that satisfies the N-detect principle of activating rare nodes identified through rareness analysis based on SCOAP values.

◾ Combining non-conflicting rare nodes using fan-in cone and PI analysis, followed by a heuristic-based vector generation method for generating an optimal number of simulation vectors for coverage analysis through payload-aware hardware Trojans.

▶  Invisible Scan for Protecting Against Scan-Based Attacks 

◾Developing a novel scan-protection architecture and corresponding design methodology for protecting the scan chain against reverse engineering attacks utilizing state-space obfuscation approach.

◾ Evaluating fault coverage after incorporating InvisibleScan on the open-source benchmarks and analyzing performance and security protection against scan-based confidentiality and RE attacks. 

◾"Mitigating Fault Attack Vulnerabilities in Block Ciphers through automated insertion of Fault Tolerant Techniques", M.Tech Thesis (2020)

◾"Developing Predictive Model to identify Risky Devices", IBM Internship (2019) 

◾"Developing an Online Course Portal", Infosys Campus Connect (2014)

◾"Eliminating noisy information and Coherent Key-phrase Extraction from web pages", B.Tech Final year project (2014)

◾Detecting Hardware Trojans using Graph Neural Networks in RTL and Gate-Level Designs (2022) 

◾Creating a basic online IDE with Live Parser (2019)

◾Sentiment Analysis of IMDB Movie Reviews (2019) 

◾Multi-user P2P Chat Application with File Sharing (2019) 

◾Predicting the helpfulness of Amazon Reviews (2018)